已知时钟信号clkin的频率为100MHz的方波信号，clkout信号的占空比为？module function(rst, clkin, clkout);input clkin, rst;output wire clkout;reg[2:0] m, n;reg clk1, clk2;assign clkout=clk1|clk2;always @(posedge clkin)begin if(!rst) begin clk1<=0; m<=0; end else begin if(m==4) m<=0; else m<=m+1; if(m<2) clk1<=1; else clk1<=0; endendalways @(negedge clkin)begin if(!rst) begin clk2<=0; n=0; end else begin if(n==4) n<=0; else n<=n+1; if(n<2) clk2<=1; else clk2<=0; endendendmodule